1. Field of the Invention
The present invention relates to a heat-resistant adhesive sheet for temporarily fixing chips used in a method for fabricating substrateless semiconductor packages that do not use a metal lead frame.
2. Description of the Related Art
Among LSI packaging technologies, Chip Size/Scale Package (CSP) technologies have recently come into attention. Among those technologies, substrateless semiconductor package technology such as Wafer Level Package (WLP) is attractive in terms of packaging density and size reduction. In a WLP fabrication method, multiple semiconductor Si wafer chips orderly arranged without the use of a substrate are encapsulated with an encapsulation resin at a time and then the wafer is diced into individual structures. Thus the method enables packages smaller than conventional ones that use a substrate to be fabricated efficiently.
In such a WLP fabrication method, chips, which are conventionally fixed on a substrate, need to be fixed on an alternative supporter. Furthermore, since the chips need to be unfixed after the chips have been encapsulated with resin and formed into individual packages, the supporter need to be removable, instead of permanent bonding fixation. Attention is therefore being given to an approach to using an adhesive sheet as such a supporter for temporarily fixing chips.
For example, Japanese Patent Laid-Open No. 2001-308116 describes a chip electronic component fabrication method that includes the steps of: attaching acrylic resin adhesion means onto a substrate, the adhesive means being adhesive before processing but the adhesion strength decreases after the processing; fixing a plurality of semiconductor chips of the same type or different types onto the adhesion means with an electrode-formed surface down; coating a whole area including interspaces between the plurality of semiconductor chips of the same type or different types with a protective material; applying predetermined processing to reduce the adhesion strength of the adhesion means and peeling off a pseudo wafer on which the semiconductor chips are fixed from the semiconductor chips; and cutting the protective material between the plurality of semiconductor chips of the same type or different types to separate the semiconductor chips or chip electronic components.
Japanese Patent Laid-Open No. 2001-313350 describes a hip electronic component fabrication method that includes the steps of: attaching acrylic resin adhesion means onto a substrate, the adhesive means being adhesive before processing but the adhesion strength decreases after the processing; fixing a plurality of semiconductor chips of the same type or different types onto the adhesion means with an electrode-formed surface down; coating a whole area including interspaces between the plurality of semiconductor chips of the same type or different types with a protective material; removing the protective material from the area from the side opposite of the electrode-formed side to the side opposite of the semiconductor chips; applying predetermined processing to reduce the adhesion strength of the adhesion means and peeling off a pseudo wafer on which the semiconductor chips are fixed from the semiconductor chips; and cutting the protective material between the plurality of semiconductor chips of the same type or different types to separate the semiconductor chips or chip electronic components.
According to these methods, the protection of the chips also protects the chips during mounting/handling after dicing and the packaging density can be improved.
Japanese Patent Laid-Open No. 2008-101183 describes a dicing/die bonding tape including an adhesive layer containing epoxy resin and acrylic rubber and a method for bonding a semiconductor device resulting from dicing onto a supporter. Obviously, the method is not intended for substrateless semiconductor devices and the adhesive layer is chosen by taking into consideration the adhesiveness to a substrate.
The following problems can arise with the following method for fabricating a substrateless semiconductor package using an adhesive sheet as a temporary supporter, which do not arise with fabrication of semiconductor packages using a lead frame.
The problems will be described below with reference to FIG. 1, which illustrates the substrateless semiconductor device fabrication method.
Multiple chips 1 are attached onto a heat-resistant adhesive sheet 2 for semiconductor device fabrication. The heat-resistant adhesive sheet 2 includes an adhesive layer 12 on one side and a substrate fixing bond layer 13 on the other side. The heat-resistant adhesive sheet 2 for semiconductor device fabrication is fixed on a substrate 3 to form a structure depicted in part (a) of FIG. 1. Alternatively, the heat-resistant adhesive sheet 2 for semiconductor device fabrication is attached onto a substrate 3 and chips 1 are fixed on the heat-resistant adhesive sheet 2 to form the structure depicted in part (a) of FIG. 1.
Then, the chips 1 on the structure depicted in part (a) are encapsulated together with an encapsulation resin 4 to form a structure illustrated in part (b) of FIG. 1.
Then, as illustrated in part (c), the heat-resistant adhesive sheet 2, together with the substrate 3, is removed from the multiple chips 1 encapsulated with the encapsulation resin 4, or the multiple chips 1 encapsulated with the encapsulation resin 4 and the heat-resistant adhesive sheet 2 are removed together from the substrate 3 and then the heat-resistant adhesive sheet 2 for semiconductor device fabrication is removed from the chips 1, thereby obtaining the multiple chips 1 encapsulated with the encapsulation resin 4.
Electrodes 5 are formed in desired positions on surfaces of the chips 1 encapsulated with the encapsulation resin 4 that are exposed on the side on which the heat-resistant adhesive sheet 2 for semiconductor device fabrication is provided, thereby forming a structure depicted in part (d).
For the step of dicing, a dicing tape 8 having a dicing ring 7 provided on its encapsulation resin 4 side as required is bonded to the structure to fix the chips 1 encapsulated with the encapsulation resin 4. The structure is diced with a dicing blade 6 as depicted in part (e) to ultimately provide multiple substrateless packages in which multiple chips are encapsulated with the resin as depicted in part (f).
During the resin encapsulation, the heat-resistant adhesive sheet 2 for semiconductor device fabrication illustrated in FIG. 2(a) can be deformed in planar directions due to expansion and elasticity of a base material layer or the adhesive layer of the heat-resistant adhesive sheet 2 for semiconductor device fabrication as illustrated in FIG. 2(b). Accordingly, the positions of the chips 1 provided on the heat-resistant adhesive sheet 2 for semiconductor device fabrication can move.
As a result, when the electrodes are provided on the chips 1, relative positional relationship between the chips 1 and the electrodes would have changed from the originally designed relationship. Furthermore, during dicing of the chips 1 encapsulated with resin, the dicing line based on the positions of the chips 1 predetermined for the dicing step would be different from the dicing line required by the actual positions of the chips 1.
Consequently, the positions of chips encapsulated in the packages resulting from dicing would vary from one package to another and a subsequent electrode formation step would not smoothly be performed and partially encapsulated packages would result.
When the heat-resistant adhesive sheet 2 for semiconductor device fabrication is peeled away from the resin-encapsulated chips, an adhesive formed on the chip side of the heat-resistant adhesive sheet 2 for semiconductor device fabrication exhibits heavy peeling from the chips and the encapsulation resin, depending on the properties of the adhesive. Therefore it can be difficult to peel off the heat-resistant adhesive sheet 2 for semiconductor device fabrication, or adhesive deposits 9 as illustrated in FIG. 3 can occur or static electricity can build up during peeling.
As peeling becomes difficult, more time is required accordingly. Heavy peeling therefore can lead to reduction in productivity. Adhesive deposits 9 can inhibit a subsequent step such as electrode formation. Static electricity build-up caused by peeling leads to a problem due to adhesion of dust in a subsequent step.
As has been described, chips can be displaced from specified positions by pressure applied during resin encapsulation because the chips are not properly held in the substrateless semiconductor package fabrication method using a heat-resistant adhesive sheet 2 for semiconductor device fabrication as a supporter for temporary fixture. When the heat-resistant adhesive sheet 2 for semiconductor device fabrication is peeled off, packages can be damaged by adhesion strength to the chips increased by curing of the encapsulation material or heat.
These problems are specific to substrateless semiconductor device fabrication methods not suffered by other methods such as the method described in Japanese Patent Laid-Open No. 2008-101183.